This invention relates generally to data communications and, more particularly, to a method for controlling isochronous data communications within a digital system having a bus architecture that complies with the IEEE-1394 Standard for a High Performance Serial Bus.
The components of a computer or other digital system are typically coupled to a common bus for communicating information to one another. Various bus architectures are known in the prior art, and each bus architecture operates according to a communications protocol that defines the manner in which data transfer between components is accomplished.
The Institute of Electrical and Electronic Engineers (IEEE) has promulgated a number of different bus architecture standards including IEEE standards document 1394, entitled Standard for a High Performance Serial Bus (hereinafter xe2x80x9cIEEE-1394 Serial Bus Standardxe2x80x9d). A typical serial bus having the IEEE-1394 standard architecture is comprised of a multiplicity of nodes that are interconnected via point-to-point links, such as cables, that each connect a single node of the serial bus to another node of the serial bus. Data packets are propagated throughout the serial bus using a number of point-to-point transactions, wherein a node that receives a packet from another node via a first point-to-point link retransmits the received packet via other point-to-point links. A tree network configuration made up of one root and several parent and child nodes, and an associated packet handling protocol ensures that each node receives every packet once. The serial bus of the IEEE-1394 Serial Bus Standard may be used as an alternate bus for the parallel backplane of a computer system, as a low cost peripheral bus, or as a bus bridge between architecturally compatible buses.
The IEEE-1394 Serial Bus supports multiple data rates, for example, 98.304 Mbit/s (referred to as the xe2x80x9cbase ratexe2x80x9d), 196.608 Mbit/s and 393.216 Mbit/s (hereafter referred to as 100, 200 and 400 Mbit/s, respectively). During start up, each node of a network configured in accordance with the IEEE-1394 Serial Bus Standard broadcasts its speed capabilities as part of a node self-identification transmission. In addition, each higher speed node (i.e., those capable of data rates in excess of the base rate) exchanges speed information with its parent at the end of the node self-identification process. In this way, each node is provided with a complete record of the speed capabilities of the nodes attached to each of its connected ports.
During normal packet transmission, a speed code is sent by a node as part of a bus arbitration phase. If a directly attached node is incapable of receiving high speed data, then it is not sent any clocked data. Instead, a data prefix is continually sent by the node accessing the bus to the slower speed node, until the higher speed node has completed sending the packet on its remaining ports. This keeps the slower attached node from arbitrating while the high speed data is sent out of the other port(s). Since the slower node propagates the data prefix to all of its other ports, all devices down stream from that node will also be kept from arbitrating.
Although this process (which is described in detail in the IEEE-1394 Serial Bus Standard) ensures that all nodes will arbitrate correctly, it is still possible for slower nodes to act as blocking points for higher speed packets. To prevent this, the initiator of a packet needs to know the speed capabilities of the nodes along the path between it and a responding node. On a fully managed bus, this information is available in the form of a speed map published by the bus manager based on data gathered from the node self-identification phase. According to the IEEE 1394 Serial Bus Standard, the speed map is an array of vectors, where each vector entry indicates the maximum data transfer rate supported between two nodes. The IEEE 1394 Serial Bus Standard specifies a format for a SPEED_MAP register but does not specify how the bus manager is to compute the vector entries for the speed map.
One prior scheme for computing the vector entries for the speed map requires that each path between nodes be traversed to determine the maximum possible transmission speed between any two nodes. To illustrate, consider the digital network illustrated in FIG. 1. Digital network 100 includes 11 nodes (0-10) interconnected via point-to-point links in a tree fashion according to the IEEE Serial Bus Standard. Each node (0-10) has an associated maximum transmission speed which in FIG. 1 is indicated in parenthesis next to the node number. The above convention where 100 represents a 98.304 Mbit/s capable node and 200 represents a 196.608 Mbit/s capable node is used here for convenience. To compute the maximum transmission speed between any two nodes, for example node 0 and node 4, the prior scheme computes:
max speed 0xe2x86x924=MIN(speed 0, speed 4)=200 Mbit/s.
Then, to compute the maximum speed between nodes 0 and 1,
max speed 0xe2x86x921=MIN(speed 0, speed 4, speed 3, speed 1)=100 Mbit/s.
In other words, for each node pair, this scheme always traverses the entire network path between the nodes of the pair to compute the maximum transmission speed. When all such paths for each node pair have been computed, a matrix such as the one shown in FIG. 2 may be generated (of course the actual speed map stored by the bus manager will comply with the format shown in the IEEE 1394 Serial Bus Standard).
This scheme for computing speed map vector entries consumes a significant amount of time, especially when there are a large number of nodes in the digital system. Accordingly, a new method for computing the speed map vector entries is needed.
Within a digital network having a bus architecture that complies with the IEEE-1394 Standard for a High Performance Serial Bus a speed map for the digital network is computed by first, computing a first speed between a first node and a second node of the digital network; and second, computing a second speed between the first node and a third node of the digital network using the computed first speed.